1. Field of the Invention
Example embodiments of the present invention relate generally to a sensing margin varying circuit and method thereof, and more particularly to a sensing margin varying circuit and method of adjusting a skew of a ready signal during a logic transition.
2. Description of the Related Art
Static random access memories (SRAMs) may store data so long as a constant supply of power is supplied thereto. Unlike dynamic random access memories (DRAMS), conventional SRAMs may require a periodic refresh operation. A typical SRAM cell may include a flip-flop storing data and two switches. Data may be read from the SRAM cell using a sense amplifier. The sense amplifier may sense a difference between a bit signal BIT and an inverted bit signal BITB respectively output through the two switches to read data stored in the SRAM cell.
FIG. 1 is a block diagram of a conventional SRAM 100. The conventional SRAM 100 may include an X decoder 101, a wordline driver 103, a dummy column unit 105, a bit cell array 107, a Y Multiplexer 109, a sense amplifier 111, an input/output unit 113, and a controller 115. Conventional operation of reading data stored in a bit cell array 107 of the SRAM 100 will now be described with reference to FIG. 1.
In conventional operation of the SRAM 100 of FIG. 1, if a clock signal CLK, an address signal ADD, an output enable signal OE, and a chip select signal CS are applied to a controller 115, the controller 115 may output a row address signal ADDX and a column address signal ADDY in response to the address signal ADD. Further, the controller 115 may output a data enable signal DEN, a data control signal DCTRL, and a precharge signal PRECHARGE obtained by inverting the data control signal DCTRL and delaying the inverted data control signal by a given period of time in response to the clock signal CLK. A write enable signal WE may also be applied to the controller 115 and the controller 115 may output an input/output enable signal IOEN.
In conventional operation of the SRAM 100 of FIG. 1, a wordline driver 103 may output a wordline signal W/L in response to a row address, which may be output from an X decoder 101 in response to the row address signal ADDX, to enable a wordline of the bit cell array 107 corresponding to the row address. Furthermore, the wordline driver 103 may transmit the data enable signal DEN and the data control signal DCTRL to a dummy column unit 105.
In conventional operation of the SRAM 100 of FIG. 1, the Y multiplexer 109 may bidirectionally connect to the bit cell array 107 and the sense amplifier 111. The Y multiplexer may also receive the column address signal ADDY and the precharge signal PRECHARGE.
In conventional operation of the SRAM 100 of FIG. 1, the input/output unit 113 may bidirectionally connect to the sense amplifier 111. The input/output unit 113 may receive the input/output enable signal from the controller 115 and receive the data input signal DIN and transmit the data output signal DOUT.
In conventional operation of the SRAM 100 of FIG. 1, the dummy column unit 105 may output a ready signal READY in response to the data enable signal DEN and the data control signal DCTRL. The controller 115 may output a sensing enable signal SENSE in response to the ready signal READY.
In conventional operation of the SRAM 100 of FIG. 1, a sense amplifier 111 may sense a difference between a bit signal BIT and an inverted bit signal BITB output from the bit cell array 107 in response to the sensing enable signal SENSE and may read data in response to the sensed difference (e.g., see (b) in FIG. 3).
As described above, the timing of sensing the levels of the bit signal BIT and the inverted bit signal BITB may depend on the time when the sensing enable signal SENSE is applied to the sense amplifier 111. The sensing enable signal SENSE may be generated in response to the ready signal READY (e.g., see (a) in FIG. 3). Accordingly, the timing of sensing the levels of the bit signal BIT and the inverted bit signal BITB may depend on the ready signal READY output from the dummy column unit 105.
FIG. 2 is a block diagram of the dummy column unit 105 of FIG. 1. The dummy column unit 105 may include a switching controller 1051, and pull-up unit 1053, an accelerating unit 1055, a first unit 1057 and a second unit 1059. Referring to FIG. 2, the dummy column unit 105 may output the ready signal READY in response to the data enable signal DEN and the data control signal DCTRL. An initial level of the ready signal READY may be set to a first logic level (e.g., a higher logic level or logic “1”) and initial levels of the data enable signal DEN and the data control signal DCTRL may be set to a second logic level (e.g., a lower logic level or logic “0”). Internal terminals FA, FB and DUMCOL of the dummy column unit 105 may be floated. Initial levels of the internal terminals FA and FB may be set to the first logic level (e.g., a higher logic level or logic “1”) and the initial level of internal terminal DUMCOL may be set to the second logic level (e.g., a lower logic level or logic “0”).
FIG. 3 illustrates a waveform timing diagram during a conventional read operation of the SRAM 100 of FIG. 1. A conventional read operation, performed by the SRAM 100 of FIG. 1, will now be described in greater detail with respect to FIGS. 1 through 3.
Referring to FIGS. 1 through 3, a node A of the dummy column unit 105 may be set to the second logic level (e.g., a lower logic level or logic “0”), and a transistor Q1 may be turned on and accelerating transistors Q2 may be turned off in response to the second logic level of the node A in the initial state. Thus, a node N from which the ready signal READY may be output, may be set to the first logic level (e.g., a higher logic level or logic “1”) in the initial state.
Referring to FIGS. 1 through 3, during the conventional read operation, the data enable signal DEN and the data control signal DCTRL may be enabled in response to the clock signal CLK, and the voltage at the node A may transition from the second logic level (e.g., a lower logic level or logic “0”) to the first logic level (e.g., a higher logic level or logic “1”). The transistor Q1 may be turned off and the accelerating transistors Q2 may be turned on in response to the first logic level at the node A.
Referring to FIGS. 1 through 3, if the accelerating transistors Q2 are turned on, a current path may be formed from the node N to a ground voltage. Accordingly, current may flow through the accelerating transistors Q2 from the node N to the ground voltage, and, thereby, the ready signal READY may transition from the first logic level (e.g., a higher logic level or logic “1”) to the second logic level (e.g., a lower logic level or logic “0”).
As shown in FIG. 3, the ready signal READY may transition to the second logic level with a given gradient (e.g., slope or skew). This gradient of the logic transition of the ready signal READY may depend on a driving capability of the accelerating transistors Q2. If the driving capability of the accelerating transistors Q2 is relatively high, current may be rapidly conducted to the ground voltage from the node N, and thus the gradient of the ready signal READY may be relatively high (e.g., the voltage may be “grounded” so as to be reduced very quickly to facilitate the transition from the first logic level to the second logic level). If the driving capability of the accelerating transistors Q2 is relatively low, the gradient of the ready signal READY may likewise be relatively low.
Referring to FIGS. 1 through 3, the wordline signal W/L may be enabled in response to the data control signal DCTRL, and data of the bit cell array 107 corresponding to the wordline W/L may be output as the bit signal BIT and the inverted bit signal BITB.
Referring to FIG. 1, the controller 115 may enable the sensing enable signal SENSE if the ready signal READY is set to the second logic level (e.g., a lower logic level or logic “0”). The sense amplifier 111 may sense the difference between the bit signal BIT and the inverted bit signal BITB in response to the enabled sensing enable signal to read data.
As described above, the difference between the bit signal BIT and the inverted bit signal BITB may be sensed or detected in response to the sensing enable signal SENSE, and the sensing enable signal SENSE may be enabled in response to the ready signal READY. Accordingly, a timing of sensing the difference between the bit signal BIT and the inverted bit signal BITB may depend on the gradient, or duration, of the ready signal READY transitioning from the first logic level to the second logic level. That is, the timing for sensing of the bit signal BIT and the inverted bit signal BITB may be determined at least in part by the driving capability of the accelerating transistors Q2 included in the dummy column unit 105. Thus, the sensing timing may be controlled by adjusting a size or number of the accelerating transistors Q2 arranged in parallel.
Conventional digital devices may be developed with portability and multi-functionality as design factors. Such conventional digital devices may include SRAMs or ROMs, which may ideally be configured for higher speed operation, higher integration and lower power consumption. In particular, a sensing margin corresponding to a period from the output of the bit signal BIT and the inverted bit signal BITB to the sensing of the difference between the bit signal BIT and the inverted bit signal BITB in response to the wordline signal W/L may be a design factor which may affect the read operation of an SRAM. Generally, the sensing margin may be determined when the SRAM or a ROM is debugged (e.g., during a fabrication process) by cutting accelerating transistors. However, if the sensing margin of the SRAM or ROM is determined to be a failure, a repair operation for the failed SRAM or ROM may not be possible with conventional repair methods.